`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/10/06 22:04:25
// Design Name: 
// Module Name: RF
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module RF(
    input clk,
    input reset,
    input [4:0] addr_a,
    input [4:0] addr_b,
    input [4:0] addr_wr,
    input we,//write enable
    input [31:0] data_wr,
    output [31:0] data_a,
    output [31:0] data_b
    );

    reg [31:0] rf [31:1];
    assign data_a = addr_a == 0 ? 0 : rf[addr_a];
    assign data_b = addr_b == 0 ? 0 : rf[addr_b];

    integer i;
    always @(posedge clk) begin
        if(reset) begin
            for(i = 0; i < 31; i = i + 1) 
                rf[i] <= 32'h0; // 复位置 0 
        end else begin
            if (we)
                rf[addr_wr] <=data_wr;
        end
    end
endmodule
